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PowerPC 600

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The PowerPC 600 family comprises the first two generations of PowerPC microprocessors for personal computers and embedded applications, including both 32-bit and 64-bit implementations. They were developed at the Somerset Design Center in Austin, Texas, a facility opened in 1992 and jointly funded and staffed by engineers from Apple, IBM and Motorola as part of the AIM alliance.

The first-generation 32-bit PowerPC 601 was introduced in 1993. It was designed as a transitional processor between IBM's POWER architecture and the PowerPC instruction set.

The second generation comprised the 32-bit PowerPC 603, the 32-bit PowerPC 604 and the 64-bit PowerPC 620. The 603, introduced in 1994, was designed for low-power applications and lower-priced computers, while the 604 targeted higher-performance desktop systems. The 620, intended for workstations and servers, was delayed until 1997, and never saw widespread adoption.

The PowerPC 600 family was succeeded by the third-generation PowerPC 700 family introduced in 1997.

Family

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PowerPC 600 series comparison[1]
601 603 603e 604 604e
Introduction October 1993 December 1994 October 1995 December 1994 July 1996
Process 600 nm 500 nm 500 nm 500 nm 350 nm
Transistors (millions) 2.8 1.6 2.6 3.6 5.1
Die size (mm2) 121 81 98 197 148
Clock speed at introduction (MHz) 60–80 75 100 120 180–200
L1 cache (KB) 32, unified 16, split 32, split 32, split 64, split
Pipeline stages 4 4 4 6 6

PowerPC 601

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PowerPC 601 prototype
PowerPC 601, produced by IBM

The PowerPC 601 was the first implementation of the 32-bit PowerPC instruction set. It was designed as a transitional processor that supported both the existing IBM POWER instructions and most of the new PowerPC instructions.[1]

Development began in mid-1991, and the first prototype chips were produced in October 1992. The processor was introduced in IBM RS/6000 workstations in October 1993 and Apple's first Power Macintosh computers in March 1994. Developed on an accelerated schedule to establish the PowerPC architecture in the market, the 601 was based on IBM's RISC Single Chip (RSC) processor and incorporated a bus interface derived from Motorola's 88110 processor, which became known as the 60x bus.[2] Use of the 60x bus allowed Apple to reuse existing designs for support ASICs it had developed for the 88110, reducing development time. The 60x bus was subsequently used in the PowerPC 603, 604, G3 and G4 processors, as well as Motorola and Freescale PowerQUICC processors.

The 601 supported symmetric multiprocessing and had a 32-bit integer unit, a floating-point unit, a branch unit and a sequencer unit, along with a memory management unit. It supported external level 2 cache and included a 32 KB unified level 1 cache. The processor initially operated at clock speeds of 50 to 80 MHz and was manufactured using IBM's 600 nm CMOS process. Its die measured 121 mm2 and contained 2.8 million transistors.[1]

PowerPC 601v

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The PowerPC 601v (v= Lower Voltage), also known as the PowerPC 601+, was introduced in 1994. It used IBM's newer 500 nm CMOS process, which reduced the die size to 74 mm2, and offered clock speeds of 90 to 120 MHz. The updated design was developed by IBM and manufactured at its facilities.[3][4][5][6]

PowerPC 603

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PowerPC 603, produced by Motorola
Die shot of a PowerPC 603

The PowerPC 603 was introduced in December 1994 alongside the 604, the first processors to implement the complete 32-bit PowerPC instruction set. It was designed as a low-cost, low-power processor for laptop computers. It offered performance comparable to the PowerPC 601 at similar clock speeds while using fewer transistors and consuming less power. The 603 featured a four-stage pipeline, five execution units and separate 8 KB instruction and data caches. Unlike the 601, it did not support symmetric multiprocessing.

The processor contained 1.6 million transistors and was manufactured by IBM and Motorola using a 500 nm CMOS process. Its die measured 85 mm2 and consumed 2.2 W at 80 MHz.[7][8][9][10][11] The 603's design later formed the basis for the PowerPC 750, marketed by Apple as the PowerPC G3.

Apple originally intended to use the 603 in its PowerBook laptop computers, but its 16 KB split cache resulted in poor performance when emulating 68K software. As a result, Apple instead used the processor in lower-cost desktop models, including the Performa 6200 and Performa 5200 series.[12][13]

PowerPC 603e

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The PowerPC 603e (e = Enhanced) was introduced in 1995. It addressed the performance limitations of the 603 by doubling the size of its level 1 cache to separate 16 KB four-way set-associative instruction and data caches. The revised processor contained 2.6 million transistors on a 98 mm2 die and operated at clock speeds of up to 200 MHz.[14][15] Its larger caches improved performance when running emulated 68K software, allowing Apple to use it in its PowerBook laptop line.

The 603e was used in a range of other systems, including the BeBox, IBM ThinkPad 800 series, accelerator cards produced by Phase5 for the Amiga, digital oscilloscopes manufactured by LeCroy, the Iridium satellite constellation and the Mark 54 Lightweight Torpedo.[16][17]

PowerPC 603ev

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The PowerPC 603ev (e = Enhanced, v= Lower Voltage) was introduced in 1995 as a lower-voltage revision of the 603e. Manufactured using a 350 nm process, it retained the 603e's 2.6-million-transistor design while reducing the die size to 78 mm2. It operated at clock speeds of up to 300 MHz and consumed up to 6 W at that speed.[18][19] The 603ev became the first mainstream desktop PowerPC processor to reach 300 MHz when it was used in the Power Macintosh 6500.

Freescale G2

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Freescale Semiconductor (created by divestiture of the Semiconductor Products Sector of Motorola in 2004) used the name G2 for the PowerPC 603e core, which became the basis for a range of embedded processors in its PowerQUICC II family of system on a chip products. These processors, designated MPC82xx, were available in configurations with clock speeds of up to 450 MHz.[citation needed]

PowerPC e300

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Freescale developed an enhanced version of the G2 core called e300 for its PowerQUICC II Pro embedded processors. The e300 added separate 32 KB instruction and data caches and other performance improvements. Processors based on the core, designated MPC83xx, operated at clock speeds of up to 667 MHz. The e300 was also used in the MPC5200B system-on-chip processor, which powered the EFIKA computer.[citation needed]

PowerPC 604

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PowerPC 604, produced by IBM

The PowerPC 604 was introduced in December 1994 alongside the PowerPC 603. It was designed as a high-performance processor for workstations and entry-level servers. It included hardware support for symmetric multiprocessing, allowing multiple processors to share system resources. Apple used it in its high-end Power Macintosh systems, while other applications included Macintosh clone computers, IBM RS/6000 workstations and servers, Amiga accelerator boards and telecommunications equipment.

The 604 is a superscalar processor capable of issuing up to four instructions per cycle. It has a six-stage pipeline and six execution units: three integer units, a floating-point unit, a branch unit and a load/store unit. The processor supports out-of-order execution and had separate 16 KB instruction and data level 1 caches. Its external interface uses a 32- or 64-bit 60x bus operating at up to 50 MHz.[1]

The 604 containes 3.6 million transistors and was manufactured by IBM and Motorola using a 500 nm CMOS process with four levels of interconnect. Its die measures 196 mm2 and consumed 14 to 17 W at 133 MHz. It operates at clock speeds between 100 and 180 MHz.[1][20][21]

PowerPC 604e

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PowerPC 604e, produced by IBM

The PowerPC 604e (e = Enhanced) was introduced in July 1996. It doubles the size of its level 1 instruction and data caches to 32 KB each and adds a dedicated condition register unit, which handled logical operations on the condition register independently of the other execution units. The processor also features improvements to its branch unit and memory subsystem, resulting in a performance increase of approximately 25% over its predecessor.[1]

The 604e containes 5.1 million transistors and was manufactured by IBM and Motorola using a 350 nm CMOS process with five levels of interconnect. Its die measures 148 mm2 in the Motorola version and 96 mm2 in the IBM version. It operates at clock speeds between 166 and 233 MHz, consumes 16 to 18 W at 233 MHz, and supports a memory bus speed of up to 66 MHz.[22][23] The 604e eventually reached 350 MHz after manufacturing moved to a 250 nm process.[1]

PowerPC 604ev "Mach5"

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The PowerPC 604ev (e = Enhanced, v= Lower Voltage), also known as the 604r or "Mach 5", was introduced in August 1997. It is a revised version of the 604e manufactured using a newer process, allowing it to operate at higher clock speeds with lower power consumption. It was manufactured by IBM and Motorola using a 250 nm CMOS process with five levels of interconnect. The die measures 47 mm2, and the processor consumes 6 W at 250 MHz. It operates at clock speeds between 250 and 400 MHz and supports a memory bus speed of up to 100 MHz.

While Apple discontinued use of the 604ev in 1998 in favor for the PowerPC 750, IBM kept using it in entry-level models of its RS/6000 computers for several years.

PowerPC 620

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The PowerPC 620 was the first implementation of the entire 64-bit PowerPC architecture. It was a second generation PowerPC alongside the 603 and 604, but geared towards the high-end workstation and server market. It was powerful on paper and was initially supposed to be launched alongside its brethren but it was delayed until 1997. When it did arrive, the performance was comparably poor and the considerably cheaper 604e surpassed it.[24] The 620 was therefore never produced in large quantities and found very little use. The sole user of PowerPC 620 was Groupe Bull in its Escala UNIX machines, but they did not deliver any large numbers. IBM, which intended to use it in workstations and servers, decided to wait for the even more powerful RS64 and POWER3 64-bit processors instead.

The 620 was produced by Motorola in a 0.5 μm process. It had 6.9 million transistors and the die had an area of 311 mm2. It operated at clock rates between 120 and 150 MHz, and drew 30 W at 133 MHz. A later model was built using a 0.35 μm process, enabling it to reach 200 MHz.[further explanation needed]

The 620 was similar to the 604. It has a five-stage pipeline, same support for symmetric multiprocessing and the same number of execution units; a load/store unit, a branch unit, an FPU, and three integer units.[25] With larger 32 KB instruction and data caches, support for a L2 cache that may have a capacity of 128 MB, and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch history table was also larger and could dispatch more instructions so that the processor can handle out-of-order execution more efficiently than the 604. The floating-point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instructions in hardware (like sqrt) made it, combined with faster and wider data buses, more efficient than the FPU in the 604.[further explanation needed]

6XX, MX, and future buses

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The system bus was a wider and faster 128-bit memory bus called the 6XX bus. It was designed to be a system bus for multiprocessor systems where processors, caches, memory and I/O was to be connected, assisted by a system control chip. It supports both 32- and 64-bit PowerPC processors, memory addresses larger than 32 bits, and NUMA environments. It was also used in POWER3, RS64, as well as 604-based RS/6000 systems (with the "Orca" bridge chip[26]).[27]

The MX IO but was utilized for IO connection in 6xx based systems. The chipsets (initially named after snakes) featured bridges between the 6xx and MX bus, with additional chips to bridge between the MX and standard IO busses.

The 6XX bus later evolved into a distributed coherent bus refereed to as the Fabric Bus, while the MX bus evolved into the GX bus(The G in reference to the project codename GigaProcessor), both utilized in the POWER4. Later GX+ and GX++ in POWER5 and POWER6 respectively. The GX bus is also used in IBM's z10 and z196 System z mainframes.

Extended family

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PowerPC 602

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The PowerPC 602 was a stripped-down version of PowerPC 603, specially made for game consoles by Motorola and IBM, introduced in February 1995.[28] It has smaller L1 caches (4 KB instruction and 4 KB data), a single-precision floating-point unit[28] and a scaled back branch prediction unit. It was offered at speeds ranging from 50 to 80 MHz, and drew 1.2 W at 66 MHz. It consisted of 1 million transistors and it was 50 mm2 large manufactured in a 0.5 μm, CMOS process with four levels of interconnect.[29]

3DO developed the M2 game console, which used two PowerPC 602,[28][30] but it was never marketed.

PowerPC 603q

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On October 21, 1996, the fabless semiconductor company Quantum Effect Devices (QED) announced a PowerPC 603-compatible processor named "PowerPC 603q" at the Microprocessor Forum. Despite its name, it did not have anything in common with any other 603. It was a from the ground up implementation of the 32-bit PowerPC architecture targeted at the high-end embedded market developed over two years. As such, it was small, simple, energy efficient, but powerful; equaling the more expensive 603e while drawing less power. It had an in-order, five-stage pipeline with a single integer unit, a double-precision floating-point unit (FPU) and separate 16 KB instruction and 8 KB data caches. While the integer unit was a brand new design, the FPU was derived from the R4600 to save time. It was 69 mm2 small using a 0.5 μm fabrication process and drew just 1.2 W at 120 MHz.[31][32]

The 603q was designed for Motorola, but they withdrew from the contract before the 603q went into full production. As a result, the 603q was canceled as QED could not continue to market the processor since they lacked a PowerPC license of their own.

PowerPC 613

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"PowerPC 613" seems to be a name Motorola had given a third generation PowerPC.[33][34][35] It supposedly was renamed "PowerPC 750" in response to Exponential Technology's x704 processor, which was designed to outgun the 604 by a wide margin. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

PowerPC 614

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Similar to PowerPC 613, the "PowerPC 614" might have been a name given by Motorola to a third generation PowerPC,[33][35] and later renamed by the same reason as 613. It has been suggested that the part was renamed "PowerPC 7400", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

PowerPC 615

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The "PowerPC 615" is a PowerPC processor announced by IBM in 1994, but that never reached mass production. Its main feature was to incorporate an x86 core on die, thus making the processor able to natively process both PowerPC and x86 instructions.[36] An operating system running on PowerPC 615 could either choose to execute 32-bit or 64-bit PowerPC instructions, 32-bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. The only operating systems that supported the 615 were Minix and a special development version of OS/2.[37]

It was 330 mm2 large and manufactured by IBM on a 0.35 μm process. It was pin compatible with Intel's Pentium processors and comparable in speed. The processor was introduced only as a prototype and the program was killed in part by the fact that Microsoft never supported the processor. Engineers working on the PowerPC 615 would later find their way to Transmeta, where they worked on the Crusoe processor. With progress having been demonstrated in the development of dynamic translation software, such as Digital's FX!32 technology, skepticism was expressed about dedicating hardware resources to running foreign binaries when such resources could be used to improve native performance instead, this also benefiting the performance of translated binaries.[38]: 94 

PowerPC 625

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"PowerPC 625" was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "RS64". The designation "PowerPC 625" was never used for the final processors.

PowerPC 630

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"PowerPC 630" was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify the POWER and PowerPC instruction sets. It was later renamed "POWER3", probably to distinguish it from the more consumer oriented "PowerPC" processors used by Apple.

PowerPC 641

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"PowerPC 641", codename Habanero, is a defunct PowerPC project by IBM in the 1994–96 timeframe. It has been suggested that was the third generation PowerPC based on the 604 processor.[39][40]

See also

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References

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  1. 1 2 3 4 5 6 7 Stokes, Jon (August 3, 2004). "PowerPC on Apple: An Architectural History, Part I". Ars Technica.
  2. ↑ "The Bus Interface for 32-Bit Microprocessors" (PDF). Motorola. 1997.
  3. ↑ Allen, M.; Becker, M (February 1993). Multiprocessing Aspects of the PowerPC 601 Microprocessor. Compcon. pp. 117–126.
  4. ↑ Becker, Michael K.; et al. (September 1993). "The PowerPC 601 Microprocessor". IEEE Micro. 13 (5): 54–68. Bibcode:1993IMicr..13e..54B. doi:10.1109/40.238002. S2CID 26895845.
  5. ↑ Moore, C.R. (February 1993). The PowerPC 601 Microprocessor. Compcon. pp. 109–116.
  6. ↑ "PowerPC 601 Microprocessor". Archived from the original on February 7, 2009.
  7. ↑ Pham et al., "A 3.0 W 75 SPECint92 85 SPECfp92 Superscalar RISC Microprocessor", ISSC Digest Of Technical Papers, pp. 212–213, Feb. 1994.
  8. ↑ Burgess et al., "The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", Proceedings of COMPCON '94, Feb. 1994.
  9. ↑ Gary et al., "The PowerPC 603 Microprocessor: A Low-Power Design For Portable Applications", Proceedings of COMPCON '94, Feb. 1994.
  10. ↑ Gerosa et al., "A 2.2 W, 80 MHz Superscalar RISC Microprocessor", IEEE Journal of Solid-State Circuits, vol. 29, pp. 1440–1454, Dec. 1994.
  11. ↑ James Kahle; Deene Ogden. "PowerPC 603 Microprocessor". IBM. Archived from the original on August 6, 1997.
  12. ↑ Linley Gwennap (February 27, 1997). "Arthur Revitalizes PowerPC Line" (PDF). Microprocessor Report. Vol. 11, no. 2. S2CID 51808955. Archived from the original (PDF) on July 30, 2018. The 603's tiny 8K caches were notoriously poor for Mac OS software, particularly for 68K emulation; even the 603e's caches cause a significant performance hit at higher clock speeds. Given Arthur's design target of 250 MHz and up, doubling the caches again made sense.
  13. ↑ Jansen, Daniel (2014). "CPUs: PowerPC 603 and 603e". Low End Mac. Retrieved 29 July 2018.
  14. ↑ "Freescale's 603e page". Freescale Semiconductor.
  15. ↑ "IBM's 603e page". Archived from the original on February 7, 2009.
  16. ↑ LeCroy 1998 Test & Measurement Products Catalog, TMCAT98 0498
  17. ↑ LeCroy 2001 Test and Measurement Products Catalog
  18. ↑ "Freescale's 603e page". Freescale Semiconductor.
  19. ↑ "IBM's 603e page". Archived from the original on February 7, 2009.
  20. ↑ Gwennap, Linley (April 18, 1994). "PPC 604 Powers Past Pentium" (PDF). Microprocessor Report. 8 (5).
  21. ↑ Song, Peter S.; Denman, Marvin; Chang, Joe (October 1994). "The PowerPC 604 RISC Microprocessor". IEEE Micro. 14 (5): 8. Bibcode:1994IMicr..14e...8S. doi:10.1109/MM.1994.363071. S2CID 11603864.
  22. ↑ "IBM's PowerPC 604e page". IBM.[dead link]
  23. ↑ "NXP's PowerPC 604e page".
  24. ↑ "IBM trashes PowerPC 620 system plans". Tech Monitor. New Statesman Media Group Ltd. August 25, 1997. Retrieved March 20, 2021.
  25. ↑ Shen, John Paul; Lipasti, Mikko H. (2013). Modern processor design: fundamentals of superscalar processors (Reissued ed.). Long Grove, Illinois: Waveland Press. pp. 302–303. ISBN 978-1-4786-0783-0.
  26. ↑ "The Orca Chip...Heart of IBM's RISC System/6000 "Value" Servers" (PDF).
  27. ↑ Thompson, Tom; Ryan, Bob. "PowerPC 620 Soars". Byte. Archived from the original on December 20, 1996.
  28. 1 2 3 "M2". Next Generation (6). Imagine Media: 36–40. June 1995.
  29. ↑ "PowerPC 602 RISC Microprocessor Hardware Specification" (PDF). Archived from the original (PDF) on 2016-08-07. Retrieved 2016-07-24.
  30. ↑ 3DO/Matsushita M2 Console Information
  31. ↑ "QED Announces PowerPC Microprocessor Technology Development In Addition To Existing MIPS Microprocessors" (Press release). Quantum Effect Devices. October 21, 1996. Archived from the original on July 12, 2007.
  32. ↑ Turley, Jim (November 18, 1996). "QED's PowerPC 603q Heads for Low Cost". Microprocessor Report: 22–23.
  33. 1 2 PowerPC revving up for next generation – Speedier RISC ahead through '97
  34. ↑ Art Arizpe -Project Manager/Engineering Manager Motorola, 1991–1996
  35. 1 2 Processor Codenames – PowerPC's
  36. ↑ Halfhill, Tom R. "Alternate Views of the 615". Byte. Archived from the original on December 20, 1996.
  37. ↑ "Microsoft killed the PowerPC 615". The Register. October 1, 1998.
  38. ↑ "DEC Unveils FX!32 Tech". Electronic News. 6 November 1995. pp. 1, 94. Retrieved 12 October 2022.
  39. ↑ "Charles Moore's resume" (PDF). Archived from the original (PDF) on July 24, 2011.
  40. ↑ Every, David K. (1999). "G3's - they just keep getting better". Archived from the original on October 10, 1999.

Further reading

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  • Weiss, Shlomo; Smith, James Edward (1994). POWER and PowerPC. Morgan Kaufmann. ISBN 1558602798. — Relevant parts: Chapter 8 (describes the PowerPC 601), and Chapter 11 (a comparison of the PowerPC 601 and Alpha 21064)
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